DRAM systems provide low-cost data storage solutions because of the simplicity of their construction. Essentially, DRAM cells are made up of a switch/transistor and a capacitor to store information in terms of charge. Therefore, the construction of DRAM cells is simple, requires much less area as compared to Static Random Access Memory (SRAM) cells, and amenable to high density integration in memory arrays and embedded systems. However, because capacitors are leaky, the charge stored in capacitors, needs to be periodically refreshed in order to retain the stored information correctly. The need for periodic and frequent refresh of the DRAM cells consumes considerable power, and renders DRAM systems unattractive for low power applications, in spite of their low cost.
Refresh operations on DRAM cells are power hungry because each time a single DRAM cell in a DRAM array needs to be refreshed, the entire row wherein the cell resides, is read out and then written back. The DRAM cells are automatically refreshed when they are read out/written back during memory read/write operations. However, the DRAM cells must be refreshed with a certain minimum frequency in order to ensure that errors are not introduced. Therefore, when memory read/writes operations do not occur within a certain period of time since the DRAM cells were last refreshed, or when the system is in a standby mode, a DRAM controller may be used to monitor the refresh rates and perform refresh cycles at the required frequency. Performing a refresh using a DRAM controller, outside of regular memory read/write operations, is also known as “self-refresh.”
Normally, in self-refresh mode, each row of a DRAM array is taken through a read out and write back process in sequence, over the course of a refresh cycle. Each of these read out and write back processes fire up word lines, a pair of complementary bit lines, sense amplifiers, etc. The minimum frequency at which refresh cycles may need to be scheduled in order to minimize errors, is usually in the order of several thousand refresh cycles per second.
Errors which may occur in DRAM arrays may be classified broadly as soft errors and hard errors. Soft errors are caused due to radioactive contaminants introduced during packaging of the embedded DRAM systems, cosmic rays, thermal neutrons, etc. Soft errors are also susceptible to the temperature of operation of the DRAM systems, such that errors are more likely at higher temperatures. Soft errors, if detected in a DRAM cell, can be rectified by just rewriting the correct data back to the DRAM cell. However, hard errors are physical defects, and may be attributable to, say, manufacturing defects. Hard errors are usually difficult to rectify.
Commonly used techniques for error detection and error correction include the use of error-correcting code (ECC) bits. ECC bits are introduced into the DRAM array as additional information, such as parity data, relating to the data stored in the DRAM array. One or more ECC bits are usually computed for each data segment, such as a byte of data, in the DRAM array. The ECC bits may be stored alongside the data in the DRAM array. When a row of data, comprising several data segments, is read out of the DRAM array, the corresponding ECC bits are read out as well. Error detection may be performed on each of the data segments within a row, using the corresponding ECC bits. If errors are detected in one or more data segments, known techniques may be used to correct the errors, and the entire row comprising correct data segments is written back to the DRAM array.
Error detection and correction in the manner described above may be performed at the direction of a processor or CPU coupled to an embedded DRAM system. As can be seen, error detection and correction also involves read out and write back operations to be performed on the DRAM array. Therefore, error detection and correction may be combined with regular read/write operations to memory as initiated by a CPU or other bus master. However, integrating this aspect of error detection and correction with regular read/write operations results in stretching the latency required for these read/write operations, which may be unacceptable in high performance systems.
Error detection and correction may also be self governed within a DRAM system, which is sometimes referred to as “self-correction.” Usually, self-correction and self-refresh are performed as separate operations. Therefore, each of these self-refresh and self-correction operations end up consuming power associated with read out and write back to the DRAM array. Some techniques attempt to tailor the frequency of self-correction based on likelihood of errors for known frequencies of self-refresh. However, even with such solutions, power consumption associated with each self-correction and self-refresh operation is not reduced. As is well known, the associated high power consumption is a serious drawback, especially for embedded systems and battery powered devices.
There is, accordingly, a need in the art for minimizing the power consumption of DRAM arrays incurred during the various memory read/write operations, refresh operations and error detection and correction operations.